(1) Field of the Invention
The present invention relates to a controller that controls memory represented by a DRAM (Dynamic Random Access Memory) and a memory system including the controller, and particularly, a controller including a synchronization circuit and a memory system including the controller.
(2) Description of Related Art
In recent high-speed memories, data is inputted and outputted in synchronization with a high-frequency clock. In particular, in a memory such as XDR DRAM (Extreme Data Rate Dynamic Random Access Memory) which is an ultra-fast memory, a plurality of bits (for example, 8 bits or 16 bits) of data are outputted in one clock. Such a memory includes bit-by-bit output terminals, and input timing based on the clock is adjusted bit by bit to control the timing gap between the data outputted from the output terminals, i.e. between bits (between DQs).
FIG. 1 shows a semiconductor storage device in which such an adjustment of input timing is performed. The semiconductor storage device comprises memory device 100, controller 200, and clock generation circuit 300.
Memory device 100 comprises output circuits 1011 to 101n that output data DQ0 to DQn-1 read out from a memory array based on a synchronization signal supplied from clock generation circuit 300 and synchronization circuit 102 that is a PLL (Phase-locked Loop) circuit and that generates a synchronization signal based on a clock from clock generation circuit 300.
Controller 200 comprises input circuits 2011 to 201n corresponding to data DQ0 to DQn-1 read out from memory device 100, delay compensation circuits 2021 to 202n corresponding to input circuits 2011 to 201n, and synchronization circuit 203. Synchronization circuit 203 is a PLL circuit and generates a synchronization signal based on the clock from clock generation circuit 300. The synchronization signal from synchronization circuit 203 is supplied to input circuits 2011 to 201n through delay compensation circuits 2021 to 202n. Input circuits 2011 to 201n correspond one to one with output circuits 1011 to 101n, and input circuits 2011 to 201n import data from corresponding output circuits in response to the synchronization signal from synchronization circuit 203. At this point, delay compensation circuits 2021 to 202n adjusts data import timing, by input circuits 2011 to 201n, of the synchronization signal from synchronization circuit 203 based on set correction values.
Although the data import timing is adjusted this way, the temperature of memory device 100 sequentially changes depending on the frequency of access to memory device 100 or depending on the use environment if a high-frequency clock is used, and the amount of timing gap due to the device characteristic change based on the temperature change also changes. Therefore, in general, the correction values set to the delay compensation circuits are periodically (for example, 10 ms intervals) adjusted to follow the temperature change.
For example, controller 200 controls writing of specific data to memory device 100 and then outputs the specific data from memory device 100. Controller 200 searches the timing of input of an expected value for each DQ and adjusts the correction values of the delay compensation circuits based on the result.
Related art of the semiconductor storage device is described in JP2005-235362A, JP2006-277892A, JP2007-080383A, JP2007-122807A, JP2007-225477A, and JP2007-305288A.
However, the present inventor has found out that the semiconductor storage device, in which the correction values associated with the input and output operations of data are periodically adjusted, has the following problems.
In general, a normal operation mode, in which a memory controller inputs and outputs data, as well as a power down mode (low power consumption mode) for reducing the power consumption can be set in a memory such as XDR DRAM.
However, since the memory controller periodically adjusts the correction values associated with the input and output operations of data, the correction values are also adjusted when the power down mode is set. The following operation is required in the adjustment of the correction values in the power down mode setting period. The mode is switched back from the power down mode to the normal operation mode, the memory controller imports the output from DQ0 to DQn-1 of the memory to adjust the correction values, and then the memory is shifted again to the power down mode.
Therefore, the normal operation mode needs to be restored even though the memory is in the power down mode setting period. There is a problem in which the power consumption increases so that the effect of the power consumption reduction by the power down mode cannot be efficiently obtained.
The following problem occurs if the correction values are not adjusted in the power down mode setting period.
Usually, the temperature of the memory gradually decreases when the mode shifts from the normal operation mode to the power down mode. Therefore, the temperature of the memory at the time of the restoration of the normal operation mode from the power down mode is low enough, compared to the temperature of the memory when the correction values are adjusted immediately preceding the shift from the normal operation mode to the power down mode. When the difference between the temperature of the memory at the time of the restoration of the normal operation mode and the temperature of the memory at the last adjustment of the correction values is large, the point where the expected value appears in the window is far off the center of the window. As a result, much time is required to adjust (search) the correction values.
In this way, if the correction values are not adjusted in the power down mode setting period, there is a problem in which much time is required to detect optimal correction values by searching DQs upon the restoration of the normal operation mode from the power down mode. Therefore, the correction values also need to be adjusted in the power down setting period.